This invention relates to timing phase detector circuits and more particularly to a circuit for obtaining a timing phase synchronous with a system period of a transmitting data signal or a receiving digital signal.
In order to transmit a digital signal or to reproduce and decode the transmitted digital signal, a timing phase signal must be generated which is in synchronism with a system period of a received digital signal.
Various types of circuits have hitherto been known as this kind of circuit for obtaining the timing phase synchronous with the system period of the transmitting digital signal, that is, as a timing phase detector circuit.
In these prior systems, system period information is detected from the receiving signal and used as a control signal for a voltage controlled oscillator (VCO). Accordingly, in the event that the receiving signal is distorted due to the fact that, for example, the pulse waveform is distorted by echoes or a pulse train forming the receiving signal changes in polarity, the detected system period information itself tends to contain jitters. Conventionally, the jitters have not been considered to be unduly serious if the system period is long but they become terribly problematic in high speed pulse transmission.
In one particular timing phase detector circuit, termed a waveform differential timing detector circuit, since the timing phase is detected at a decision phase which coincides with a point of time t at which the amplitude of the receiving pulse waveform becomes a maximum, the receiving pulse is sampled at time points t+.DELTA.and t-.DELTA.t, where .DELTA.t is an interval of time sufficiently less than the system period, and the decision phase t is controlled by controlling the difference between the two sampled values such that it converges toward zero.
Advantageously, the waveform differential timing detector circuit does not require a highly accurate element such as a tank circuit and hence its characteristics will not be degraded under the influence of temperature variations and aging. In addition, there is no need for providing phase setting (presetting, in design, of the difference between a decision phase exhibited by the tank circuit and an actually optimum decision phase) which is otherwise indispensable for the use of the tank circuit.
However, the waveform differential timing detector circuit does away with taking into consideration jitters attributable to degraded waveform caused by echoes or pattern jitters attributable to finiteness of .DELTA.t.